1. Field of the Invention
The present invention relates to a current mirror device for an integrated circuit, and in particular to an integrated circuit arrangement comprising a reference-current source device for providing a reference current, and comprising a current mirror device for mirroring the reference current to an output current.
In such a circuit arrangement, a reference current provided in the region of the integrated circuit can provide the basis for a multitude of currents which are required in other regions of the integrated circuit, wherein in each instance these mirrored currents are in a predetermined ratio to the reference current.
2. Description of the State of the Art
FIG. 1 shows a known current mirror device comprising a first FET Q1, operated in saturation, whose channel carries the reference current Iin; as well as a second FET Q2, operated in saturation, whose channel carries the output current Iout; wherein the gate connections of the two FETs are interconnected in order to ensure identical control voltages (gate-source voltages) at these two FETs. Identical control voltages on the FETs result in the reference current Iin being mirrored to the output current Iout, i.e. they result in a current flowing in the channel of the FET Q2, with said current being in a fixed ratio to the reference current Iin. This ratio Iout/Iin depends on the design, in particular on the dimensions, of the FETs Q1 and Q2.
In the simplest case, for example if the FETs Q1 and Q2 are of identical design, Iout/Iin=1, or Iout=Iin applies.
In a way which is well known, such a current mirror can also mirror the reference current to a multitude of output currents, in that the gate voltage which is present at the FET Q1 due to the presence of the reference voltage Iin is not only used as a gate voltage for a second FET Q2 but as a gate voltage for a multitude of such FETs.
It is also known to bring together in one node several currents which have been generated by mirroring, as mentioned above, in order to generate an output current as the sum of these mirrored currents.
The output impedance which the load that is driven by the output current sees, is a first performance characteristic of a current mirror, which performance characteristic is important in practical application. The small-signal output impedance of the current mirror rout shown in FIG. 1 is defined as vout/iout, with vout and iout representing the small-signal sizes of the output voltage Vout and of the output current Iout. Ideally, this output impedance rout is infinite. In order to implement this approximately, it is essential that the FETs Q1 and Q2 are operated in saturation. In this operating range, as is well known, the drain current of a FET hardly deviates from the drain-source voltage.
In this context, the term xe2x80x9csaturationxe2x80x9d refers to an operating range in which the following relationship applies:
Vds greater than Vgsxe2x88x92Vth
wherein
Vds=drain-source voltage
Vgs=gate-source voltage (control voltage)
Vth=threshold voltage
If an effective control voltage Vgt is defined as Vgsxe2x88x92Vth, then the condition for saturation can also be defined as Vds greater than Vgt.
In the current mirror shown in FIG. 1, saturation of the FET Q1 is ensured by the connection between drain and gate of Q1 (analogous to the respective circuit in the case of bipolar transistors, Q1 is designated xe2x80x9cdiode-switchedxe2x80x9d). Consequently, due to the drain-source voltage inevitably dropping at the FET Q1, the possible range of the drain potential of Q1 is limited. Said drain-source voltage poses a problem in particular in the design of the driving current source Iin (limited xe2x80x9cinput voltage rangexe2x80x9d).
The deviation available to the output current, i.e. the range of the output voltage for which range the current mirror operates at the desired current-transformation ratio, is a second important performance characteristic of a current mirror. In the current mirror shown in FIG. 1, this voltage deviation is limited in that at the channel of the FET Q2 inevitably there is a drain-source voltage drop.
FIG. 2 shows a current mirror which in the literature is often referred to as a xe2x80x9ccascode current mirrorxe2x80x9d, which has a considerably increased output impedance rout. This is achieved in that, as shown in FIG. 2, cascoded FETs are arranged in series to the FETs Q1 and Q2, with said cascoded FETs, for the reasons explained above, also having to be operated in saturation. Furthermore, for the purpose of achieving an increased output impedance, a number of modifications of the current mirror shown in FIG. 2 are known, e.g. a feedback current mirror, source degeneration current mirror, etc. These current mirrors are associated with the disadvantage that the output voltage deviation (as well as the input voltage range) is further reduced. In many cases, the option of a multiple-cascoded current mirror (e.g. double cascode current mirror) in which one or several additional cascode stages are arranged, although an imaginable and known option, is not useable in practical application due to the operating voltages of integrated circuits having continuously decreased over time.
It is the object of the present invention to improve an integrated circuit arrangement of the type described above such that for a predetermined output impedance, the output voltage deviation is increased, or for a predetermined output voltage deviation the output impedance is increased.
This object is met by an integrated circuit arrangement with a specially designed reference-current supply on the first FET. The dependent claims relate to advantageous improvements of the invention.
It is important for the invention that at a channel connection of the first FET, a node for generating the reference current carried by the channel of this FET is provided from several reference-current components, wherein the reference-current components are provided at the node by the reference-current source device, and at least one of the reference-current components is carried by way of a resistance element which is connected between the node and the gate connection of the first FET.
The reference-current component carried by way of a resistance element causes a voltage drop at this resistance element, and thus a voltage between the channel connection and the gate of the first FET, which results in an increase in the useable output voltage deviation.
A particularly simple embodiment provides for the reference-current source device, to supply two reference-current components at the node, and for one of the two reference-current components to be carried by way of the resistance element. In this arrangement, the two current components can be provided e.g. to be different from each other by a factor of max. 2, in particular to be approximately identical in size. In certain cases this can increase the accuracy of current mirroring and can simplify the design of the current source device.
Any component which causes a voltage drop as a result of a current flow through the component is suitable as a resistance element.
In a preferred embodiment the resistance element is formed by the channel of a further FET. In this way it is possible to particularly easily and reliably achieve a desired voltage drop at the resistance element within the framework of the production technology used (component matching relative to the first and second FET). To set the resistance behaviour, the gate connection of this further FET can be subjected to a predetermined voltage, preferably a voltage for which this FET is operated in saturation when the current mirror is operative. Furthermore, the gate connection can be connected to a channel connection of this FET (diode circuit).
A further particularly preferred embodiment provides for the current mirror device to comprise a third FET which is serially connected to the first FET and operated in saturation, with the channel of said third FET carrying at least one of the reference current components, and, wherein the current mirror device, serially to the second FET, comprises a fourth FET operated in saturation, with the channel of said fourth FET carrying the output current, wherein the gate connections of the third FET and of the fourth FET are interconnected in order to ensure identical control voltages at these two FETs. This application, achieved with the invention, of the voltage difference between a channel connection and the gate connection of the first FET in the case of a cascoded current mirror device is particularly advantageous because is it possible not only to achieve the considerably increased output impedance of a cascoded current mirror, but also to reduce the reduction in the output deviation which results in the state of the art from doing so. This makes it possible for example to use cascoded current mirror devices in integrated circuits whose particularly low supply voltages hitherto had made it impossible to use a cascoded current mirror.